The present invention relates, in general, to the field of integrated circuit (IC) devices. More particularly, the present invention relates to a high speed power-gating technique for integrated circuit devices incorporating a Sleep Mode of operation.
Power-gating has been used in conjunction with various circuits to reduce Sleep Mode power. Conventionally, this is achieved by adding transistors in the VCC and VSS supply paths to the circuit. These power gate transistors are turned “on” during an Active Mode of operation and turned “off” during Sleep Mode to reduce the total static current due to transistor “off” current. Typically, the gate terminals of the power gate transistors are forced to higher than VCC (in the case of P-channel devices) or lower than VSS (in the case of N-channel devices) voltage levels so that their voltage gate-to-source (VGS) is negative. This reduces the “off” current of these transistors significantly.
However, since there are often a large number of circuits coupled to these power gate transistors, and all of these circuits may be switching at about the same time, the current surge through the power gate transistors during an Active Mode operation ends up being very large. This current surge causes a voltage drop across the power gate transistors which tends to have the same effect as reducing the level of VCC, thereby degrading performance. Furthermore, these power gate transistors must, of necessity, be made extremely large to avoid degrading circuit speed too much, (although such degradation nonetheless occurs to at least some extent) thereby consuming a great deal of on-chip area.
In write data driver circuits associated with integrated circuit memory arrays, this conventional approach is effective if the power-gate transistors can be shared by a significant number of circuits that do not switch at the same time. However, in the case of integrated circuit memory devices and those incorporating embedded memory where there are a large number of write data drivers (for example up to 256 or more) that switch at the same time, the current surge going through the NMOS power-gate transistor is very large. This results in a voltage drop across the power-gate transistor which limits the switching speed of the output stage of the write data driver circuits.